(1) Field of the Invention
The present invention relates to a trigger pulse generator which generates trigger pulses synchronized with the leading edges and trailing edges of an input signal and used, for example, in a semiconductor memory device.
(2) Description of the Prior Art
In a semiconductor memory device such as a static-type random access memory device, if the potentials of the bit lines of each bit line pair are preset at the same high level when the input address signals are changed and the readout of information is effected, it is possible to obtain a short access time. In order to effect presetting of the bit line potentials, transistor switches are connected between the bit lines of each bit line pair and the voltage source, and the transistor switches are temporarily turned on under the control of the trigger pulses.
FIG. 1 is a conventional trigger pulse generator for generating trigger pulses used for the above-mentioned purpose. In FIG. 1, 10 designates an amplifier which outputs a non-inverted output signal B, i.e., A', and an inverted output signal C of the input signal A, i.e., A'; 12, 14, 16, and 18 are inverters; 20 is a NOR gate; and 22 and 24 are capacitors which are, respectively, connected between a non-inverting output terminal T.sub.1 and ground and between an inverting output terminal T.sub.2 and ground. If the trigger pulse generator of FIG. 1 is used in a semiconductor memory device, the input signal A is an address signal and the amplifier 10 is an address inverter. Although the detailed circuit structure of the amplifier 10 is not shown in the drawing, each of the output stages of the amplifier 10 usually comprises an enhancement-type or depletion-type field effect transistor (FET) which serves as a load element and whose gate and drain are commonly connected to each other, and an enhancement-type driver FET which is connected in series with the load element and which receives an input signal. When the input signal A illustrated in FIG. 2 is applied to the input terminal of the amplifier 10, the amplifier 10 outputs the non-inverted output signal A' and the inverted output signal A'. Since the capacitors 22 and 24 are charged and discharged by these output signals, the waveforms of the output signals of the output terminals T.sub.1 and T.sub.2 become as shown by B and C of FIG. 2. The discharge of electric charges in the capacitor 22 or 24 is effected rapidly through the above-mentioned driver FET which is turned on, and, therefore, each of the output signals falls quickly. Charging of the capacitor 22 or 24 is effected gradually through the load FET so that each of the output signals rises slowly. The two-stage inverters 12, 16 and 14, 18 effect wave shaping of the output signals B and C and output rectangular wave signals B' and C' whose rising edges are delayed by the time period t from the rising edge or the falling edge of the input signal A. The signals B' and C' are supplied to the NOR gate 20, and the NOR gate 20 outputs trigger pulses D, each of which is generated at the falling edge or the rising edge of the input signal A and each of which has a rectangular shape and a small width.
However, the above-mentioned conventional trigger pulse generator has a disadvantage in that the width of each of the output pulses varies in accordance with the change in the power supply voltage V.sub.cc. The high level of the output signals B and C from the amplifier 10 is substantially equal to the power supply voltage V.sub.cc and the low level of the output signals B and C is substantially equal to ground level. Therefore, when the power supply voltage V.sub.cc falls, the waveforms of the output signals B and C become as shown by the dotted lines, so that the width of the output trigger pulse D becomes large. It is preferable that the width of the output trigger pulse D be constant, and it not vary with the variation of the power supply voltage. For example, in a circuit generating clock pulses at the falling edges of the above-mentioned output trigger pulses D, the generated timing of the clock pulses unstably varies in accordance with the variation of the power supply voltage.
In the trigger pulse generator of FIG. 1, since the timing of the rising edges of the output signals B and C of the amplifier 10 is delayed by the capacitors 22 and 24, it is necessary to use capacitors having a large capacitance in order to generate the trigger pulses D, each having a large pulse width. Therefore, when the trigger pulse generator of FIG. 1 is formed in an integrated circuit, it is necessary to use separate discrete capacitors outside the integrated circuit.